Computer Organization and Architecture Question Bank with answers

 

Questions 81 To 90

81.	A machine cycle refers to (a) Fetching an instruction (b) Clock speed (c) Fetching, decoding and executing  an instruction (d) Executing and instruction (e) Decoding an instruction.
82.	The System bus is made up of (a) Control bus (b) Address bus (c) Both Control bus and Address bus (d) Control bus, Data bus and Address bus (e) Data bus.
83.	The code used to boot up a computer is stored in (a) RAM (b) ROM (c) PROM (d) EPROM (e) EEPROM.
84.	In accessing a disk block the longest delay is due to (a) Rotation time (b) Seek time (c) Transfer time (d) Clock speed (e) Access time.
85.	Which of the following is/are not part(s) of the CPU? (a) ALU (b) The Control unit (c) The Registers (d) System bus (e) All of the above.
86.	Memory mapped  I/O  involves transferring of (a) Information between memory locations (b) Information between registers and memory (c) Information between CPU and I/O devices (d) Information between CPU and  Memory (e) Information between I/O devices and CPU.
87.	Name the type of memory that can be erased with the electric discharge? (a) ROM (b) EPROM (c) RAM (d) EEPROM (e) PROM.
8.	What is the units for measuring the CPU performance? (a) BPS (b) MIPS (c) MHz (d) VLSI (e) KHz.
89.	The read/write line belongs to (a) The data bus (b) The control bus (c) The address bus (d) CPU bus (e) System bus.
90.	Busy waiting is a technique (a) To allow the CPU wait for a busy device (b) To allow a busy device wait for the CPU (c) To keep an idle device busy (d) To improve CPU performance (e) To keep a device busy.

Answers

81.	Answer :   (c) Reason  :  A machine cycle refers to Fetching, decoding and executing  an instruction.
82.	Answer :   (d) Reason  :  System bus consists of a Control bus, Data bus and a Address bus.
83.	Answer :   (b) Reason  :  The bootable code is stored in ROM.
84.	Answer :   (e) Reason  :  Access time.
85.	Answer :   (d) Reason  :  System bus is not a part of a cpu .
86.	Answer :   (e) Reason  :  Memory mapped I/O involves transferring information between I/O devices and CPU .
87.	Answer :   (d) Reason  :  EEPROM is the type of memory whose contents is erased with the passage of electiricity.
88.	Answer :   (c) Reason  :  CPU performance is measured in MHz
89.	Answer :   (c) Reason  :  The read / write line belongs to the address bus.a
90.	Answer :   (a) Reason  :  Busy waiting is to allow the CPU wait for a busy device.

Questions 91 To 100

91.	Which of the following Addressing Modes specifies a register which contains the memory address of the operand? (a) Indirect Addressing Mode (b) Register Addressing Mode (c) Register Indirect Addressing Mode (d) Index Addressing  Mode (e) Base Address Register Addressing Mode.
92.	Identify the term, which indicate a set of Logical Addresses. (a) Memory space (b) Disk space (c) Address space (d) Location (e) Page frame.
93.	Which of the following is false related to Stack? (a) Stack Pointer points to the top most element of the stack (b) Only PUSH and POP operations are applicable (c) Implements FIFO (d) Useful for nested loops, subroutine calls etc (e) Efficient for arithmetic expression evaluation.
94.	Which of the following is the method in which the unit receiving the data responds with another control signal? (a) Timing sequence (b) Synchronous (c) Strobe (d) Short message service (e) Handshaking.
95.	What is the page replacement algorithm in which there is a replacement of a page, which will not be used for the longest period of time? (a) MFU (b) LRU (c) OPT (d) FIFO (e) LFU.
96.	Of the following, what is an input device for which finger shows the cursor movement? (a) Mouse (b) Scanner (c) Microphone (d) Trackball (e) Glide pad.
97.	Consider the following unsigned  decimal numbers: i.       6543. ii.      4444. What is the result after subtracting (i) by taking the 10's complement of (ii)? (a) 2098 (b) 2099 (c) 2096 (d) 2097 (e) 2095.
98.	What is the octal equivalent of given binary number? 011001 (a) 32 (b) 31 (c) 34 (d) 33 (e) 35.
99.	Which of the following describes the Mnemonic SPA? (a) Skip If (Address Resister) Positive (b) Skip If (Accumulator) Positive (c) Skip If (Adder-Subtractor) Positive (d) Skip If (Associative Mapping) Positive (e) Skip If (Assembler) Positive. lala
100.	Which of the following is correct related to the circuit diagrams? (a) Sequential circuit is an interconnection of only logic gates (b) Sequential circuit is an interconnection of only flip flops (c) Combinational circuit is an interconnection of  logic gates (d) Combinational circuit is an interconnection of flip flops (e) Part of a combinational circuit is a sequential circuit.

Answers

91.	Answer :       (c) Reason:  Addressing mode that specifies a register which contains the memory address of the operand is  Register Indirect Addressing Mode.
92.	Answer :       (c) Reason:  Address space indicate a set of Logical Addresses.
93.	Answer :       (c) Reason:  Stack does not Implement FIFO but implements LIFO.
94.	Answer :       (e) Reason:  Handshaking is the method in which the unit receiving the data responds with another control signal.
95.	Answer :       (c) Reason:  The page replacement algorithm in which there is a replacement of a page, which will not be used for the longest period of time is OPT.
96.	Answer :       (e) Reason:  The input device for which finger shows the cursor movement is Glide pad.
97.	Answer :       (b) Reason:  6543- 4444= 2099
98.	Answer :       (b) Reason:  The octal equivalent of  011001 =31.
99.	Answer :       (b) Reason:  SPA stands for Skip If (Accumulator) Positive
100.	Answer :       (c) Reason:  Combinational circuit is an interconnection of logic gates.

Questions 101 To 110

101.	Of the following, identify the memory usually written by the manufacturer. (a) RAM (b) DRAM (c) SRAM (d) ROM (e) Cache Memory.
102.	What does D stands for in D-flip flop? (a) Direct (b) Don’t care (c) Double (d) Delay (e) Data.
103.	Consider that the program is executed from main memory until it attempts to reference a page that is still in auxiliary memory. Identify this condition. (a) Page Found (b) Page Fault (c) Page Hit (d) Page Miss (e) Page Replace.
104.	DMA stands for (a) Direct Memory Address (b) Direct Main Address (c) Direct Memory Access (d) Direct Main Access (e) Device Memory Access.
105.	What is the symbol to represent a state in the state diagram?
106.	Consider DR ← M [AR], Identify the operation. (a) Arithmetic Operation (b) Shift Operation (c) Memory Write (d) Memory Read (e) Memory Cycle.
107.	A computer has memory of 256k words of 32 bits each, how many bits are required to specify the address part? (a) 16 bits (b) 12 bits (c)   8 bits (d) 18 bits (e) 10 bits.
108.	Which one of the following can be called as a peripheral? (a) Control Unit (b) Arithmetic Unit (c) Speakers (d) Logic Unit (e) Main Memory.
109.	is a symbol for (a) OR (b) XOR (c) AND (d) NAND (e) NOR.
110.	What is the operation sets to 1 the bits in one register where there are corresponding 1’s in the second register? (a) Selective Complement (b) Selective Clear (c) Selective Set (d) Mask (e) Insert.

Answers

101.	Answer :       (d) Reason:  ROM is  the memory usually written by the manufacturer.
102.	Answer :       (e) Reason:  D stands in D-flip flop stands for Data.
103.	Answer :       (b) Reason:  The program is executed from main memory until it attempts to reference a page that is still in auxiliary memory called Page Fault.
104.	Answer :       (c) Reason:  DMA stands for Direct Memory Access.
105.	Answer :       (b) Reason:  The symbol to represent a state in the state diagram is
106.	Answer :       (d) Reason:  DR ← M [AR] is Memory Read.
107.	Answer :       (d) Reason:  A computer has memory of 256k words of 32 bits each, 18 bits  are required to specify the address part.
108.	Answer :       (c) Reason:  Speakers can be called as a peripheral.
109.	Answer :       (c) Reason:  is a symbol for AND.
110.	Answer :       (c) Reason:  Selective Set is the operation sets to 1 the bits in one register where there are corresponding 1’s in the second register.